Electronic circuits, including microprocessors, have in recent years become increasingly powerful and fast. As circuit frequencies increase, noise on power supply and ground lines coupled to the microprocessor increasingly becomes a problem. This noise can arise due to, for example, well known inductive and capacitive parasitics.
Decoupling capacitors are often used to reduce this noise on power supply and ground. Ideally, the decoupling capacitors are connected between the power supply and ground lines. Additionally, the decoupling capacitors are placed as close as possible to circuits, such as input/output (IO) devices, of the microprocessor that are susceptible to noise. The decoupling capacitor may be integrally formed on the microprocessor. However, such a capacitor would be costly to manufacture using prior art methodologies. In particular, a typical processing sequence would require a deposition, patterning, and etch of a first dielectric layer, to isolate underlying metal layers of the microprocessor substrate from the capacitor. Depositing, patterning and etching a first metal layer could form, following the first dielectric layer, the lower plate of the capacitor. Then, depositing, patterning and etching a second dielectric layer could form the interplate dielectric. Next, a second metal layer forming the second plate of the capacitor could be deposited, patterned and etched followed by a final dielectric layer deposition, patterning and etch to isolate the capacitor. The various patterning and etch steps are needed in order to connect one plate of the capacitor to power and the other to ground, as well as to provide vias for interconnection from one or more metal layers below the capacitor to one or more metal layers above the capacitor.
As an alternative, n-channel or p-channel metal oxide semiconductor field effect transistor can be integrally formed on microprocessors and coupled to function as decoupling capacitors. Hereinafter, n-channel metal oxide semiconductor field effect transistors will be referred to as n-channel FETs, while p-channel metal oxide semiconductor field effect transistors will be referred as to as p-channel FETs. In one configuration, the gate of the integrally formed n-channel or p-channel FET is coupled to one of the power or ground lines or, while the drain and source of the n-channel or p-channel FET is coupled the other of the power or ground lines of the microprocessor.
N-channel or p-channel FET operation is subject to limitations. More particularly, the voltage Vgd between the gate and drain of FETs or the voltage Vgs between the gate and source of FETs should not exceed a gate oxide voltage limit Vlimit. If Vgs or Vgd exceeds Vlimit in either of a p-channel or n-channel FET, damage can occur to the FET that renders it permanently inoperable.
Vlimit (also known as gate oxide integrity) depends on failure in time (FIT) rate and/or the gate area of the FET. The FIT rate requirement is provided by a system design specification. For FETs manufactured using 0.18-micron process rules, Vlimit is around 1.7 v. The sizes of FETs, including gate areas thereof, in microprocessors continue to reduce as semiconductor manufacturing technology advances. As the gate areas of FETs reduce, so does Vlimit. Thus, if the voltage difference between the power supply and the ground node remains the same while the size of the n-channel or p-channel FETs reduces, n-channel or p-channel FETs can no longer be used as decoupling capacitors between power and ground lines of the microprocessor as described above.